diff -urN linux-2.6.16.9/arch/arm/Kconfig linux-2.6.16.9-apm/arch/arm/Kconfig --- linux-2.6.16.9/arch/arm/Kconfig 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/arch/arm/Kconfig 2006-04-24 10:16:23.000000000 +0300 @@ -246,6 +246,11 @@ Say Y here if you intend to run this kernel on an Atmel AT91RM9200-based board. +config ARCH_RVISS + bool "RealView Instruction Set Simulator" + help + Say Y here if you intend to run this kernel on the RealView ISS. + endchoice source "arch/arm/mach-clps711x/Kconfig" diff -urN linux-2.6.16.9/arch/arm/kernel/head.S linux-2.6.16.9-apm/arch/arm/kernel/head.S --- linux-2.6.16.9/arch/arm/kernel/head.S 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/arch/arm/kernel/head.S 2006-05-17 19:13:26.000000000 +0300 @@ -296,7 +296,17 @@ add r3, r3, #1 << 20 str r3, [r0, #4]! @ KERNEL + 2MB add r3, r3, #1 << 20 - str r3, [r0, #4] @ KERNEL + 3MB + str r3, [r0, #4]! @ KERNEL + 3MB + add r3, r3, #1 << 20 + str r3, [r0, #4]! @ KERNEL + 4MB + add r3, r3, #1 << 20 + str r3, [r0, #4]! @ KERNEL + 5MB + add r3, r3, #1 << 20 + str r3, [r0, #4]! @ KERNEL + 6MB + add r3, r3, #1 << 20 + str r3, [r0, #4]! @ KERNEL + 7MB + add r3, r3, #1 << 20 + str r3, [r0, #4] @ KERNEL + 8MB /* * Then map first 1MB of ram in case it contains our boot params. diff -urN linux-2.6.16.9/arch/arm/mach-rviss/Kconfig linux-2.6.16.9-apm/arch/arm/mach-rviss/Kconfig --- linux-2.6.16.9/arch/arm/mach-rviss/Kconfig 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/arch/arm/mach-rviss/Kconfig 2006-01-30 22:40:21.000000000 +0200 @@ -0,0 +1,13 @@ +if ARCH_RVISS + +menu "RVISS Options + +# CPU type + +# IO addresses + +# CPU speed + +endmenu + +endif diff -urN linux-2.6.16.9/arch/arm/mach-rviss/Makefile linux-2.6.16.9-apm/arch/arm/mach-rviss/Makefile --- linux-2.6.16.9/arch/arm/mach-rviss/Makefile 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/arch/arm/mach-rviss/Makefile 2006-01-26 15:39:08.000000000 +0200 @@ -0,0 +1,4 @@ +# +# RVISS=RealView Instruction Set Simulator +# +obj-y := rviss.o diff -urN linux-2.6.16.9/arch/arm/mach-rviss/Makefile.boot linux-2.6.16.9-apm/arch/arm/mach-rviss/Makefile.boot --- linux-2.6.16.9/arch/arm/mach-rviss/Makefile.boot 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/arch/arm/mach-rviss/Makefile.boot 2006-02-14 18:50:10.000000000 +0200 @@ -0,0 +1,6 @@ +# +# RVISS can provide RAM anywhere +# +zreladdr-y := 0xc0008000 +params_phys-y := 0xc0000100 + diff -urN linux-2.6.16.9/arch/arm/mach-rviss/rviss.c linux-2.6.16.9-apm/arch/arm/mach-rviss/rviss.c --- linux-2.6.16.9/arch/arm/mach-rviss/rviss.c 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/arch/arm/mach-rviss/rviss.c 2006-05-17 15:49:58.000000000 +0300 @@ -0,0 +1,475 @@ +/* -*- linux-c -*- + * linux/arch/arm/mach-rviss/rviss.c + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Support for ARM RealView Instruction Set Simulator + * + * Written based on ARMulator documentation: + * + * The RVISS user guide + * http://www.arm.com/pdfs/DUI0207C_realview_armulator_iss_ug.pdf + * ARM application note 32 + * http://www.arm.com/pdfs/AppNote32_ARMulator.zip + * Reference Peripheral Specification + * http://www.arm.com/pdfs/DDI0062D_refper-spec.pdf + * + */ + +#include /* ARRAY_SIZE etc */ +#include /* __init etc */ +#include /* struct resource */ +#include /* struct list_head needed by struct irqchip */ +#include /* irqreturn_t etc */ +#include /* struct console etc */ +#include /* struct tty_struct etc */ +#include /* PAGE_SHIFT, needed by __phys_to_pfn */ +#include /* SZ_... */ +#include /* struct map_desc */ +#include /* struct irqchip */ +#include /* timer_tick() */ +#include /* MACHINE_START */ +#include /* MACH_TYPE_RVISS */ + +static volatile unsigned long *rviss_tube = (volatile void *)0xed800020; + +static void +rviss_tube_write(const char *s, + unsigned count) +{ + int i; + for (i = 0; i < count; ++i) + { + /* Seems that '\r' clears the line just written to the + * RealView debugger StdIO - lets just skip em.. + */ + if (*s != '\r') + *rviss_tube = *s; + ++s; + } +} + +static int +rviss_tty_open(struct tty_struct *tty, struct file *filp) +{ + return 0; +} + +static int +rviss_tty_write(struct tty_struct *tty, const unsigned char *buf, int len) +{ + rviss_tube_write(buf, len); + return len; +} + +static int +rviss_tty_write_room(struct tty_struct *tty) +{ + return 512; +} + +static int +rviss_tty_chars_in_buffer (struct tty_struct *tty) +{ + return 0; +} + +static struct tty_operations rviss_tty_ops = { + .open = rviss_tty_open, + .write = rviss_tty_write, + .write_room = rviss_tty_write_room, + .chars_in_buffer = rviss_tty_chars_in_buffer, +}; + +static struct tty_driver *rviss_tty_driver; + +static struct tty_driver * +rviss_console_device(struct console *c, int *index) +{ + *index = c->index; + return rviss_tty_driver; +} + +static void +rviss_console_write(struct console *co, + const char *s, + unsigned int count) +{ + rviss_tube_write(s, count); +} + +static int __init +rviss_tty_init(void) +{ + int err; + struct tty_driver *driver; + + driver = alloc_tty_driver(1); + if (!driver) + return -ENOMEM; + driver->driver_name = "tube"; + driver->name = "ttyRVISS"; + driver->major = 666; + driver->minor_start = 0; + driver->type = TTY_DRIVER_TYPE_SYSTEM; + driver->subtype = SYSTEM_TYPE_SYSCONS; + driver->init_termios = tty_std_termios; + tty_set_operations(driver, &rviss_tty_ops); + err = tty_register_driver(driver); + if (err) + { + put_tty_driver(driver); + return err; + } + rviss_tty_driver = driver; + return 0; +} +late_initcall(rviss_tty_init); + +static struct console rviss_console = { + .name = "ttyRVISS", + .write = rviss_console_write, + .device = rviss_console_device, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +static int __init +rviss_console_init(void) +{ + register_console(&rviss_console); + return 0; +} +console_initcall(rviss_console_init); + +/* RVISS machine_desc.init_machine */ +static void __init +rviss_init(void) +{ +} + +/* For the time being, use the default physical addresses and + * map them to start at virtual 0xe0000000 + */ +static struct map_desc rviss_io_desc[] __initdata = { + /* Interrupt controller */ + { 0xea000000, __phys_to_pfn(0x0a000000), SZ_4K, MT_DEVICE }, + /* Timer */ + { 0xea800000, __phys_to_pfn(0x0a800000), SZ_4K, MT_DEVICE }, + /* Tube */ + { 0xed800000, __phys_to_pfn(0x0d800000), SZ_4K, MT_DEVICE }, +}; + +/* RVISS machine_desc.map_io */ +static void __init +rviss_map_io(void) +{ + iotable_init(rviss_io_desc, ARRAY_SIZE(rviss_io_desc)); +} + +/* Resource descriptor for the RVISS default interrupt controller model */ +static struct resource irq_resource = { + .name = "IRQ (RVISS interrupt controller)", + .start = 0x0a000000, + .end = 0x0a000200, + .flags = IORESOURCE_MEM, +}; + +/* The virtual address for the interrupt controller */ +static volatile unsigned long *rviss_intc = (volatile void *)0xea000000; + +/* The RVISS documentation is really terse about + * the interrupt controller. It more or less just lists + * the registers: + * + * base + 0x000: IRQ status, ro + * base + 0x004: IRQ raw status, ro + * base + 0x008: IRQ enable read/set, rw + * base + 0x00c: IRQ enable clear, wo + * base + 0x010: IRQ soft, wo + * base + 0x100: FIQ status, ro + * base + 0x104: FIQ raw status, ro + * base + 0x108: FIQ enable read/set, rw + * base + 0x10c: FIQ enable clear, wo + * + * One really needs to consult the "ARM DDI 0062D" + * reference peripheral spec, which lists + * - enable register, ro, 1 means enabled + * - enable set, wo, 1 means enable + * - enable clear, wo, 1 means disable + * - source status, ro, 1 means req active (prior to masking) + * - interrupt request, ro, 1 means req active (after masking) + * - programmed int, wo, generate interrupt + * + * So what would one deduce from the above? Status could be req status + * after masking and raw status before masking. Enable, clear and soft + * are less ambiguous. + * + * The interrupt sources in RVISS are (by default): + * - 0: FIQ + * - 1: soft + * - 2: communication channel rx + * - 3: communiaction channel tx + * - 4: timer 1 + * - 5: timer 2 + */ + +/* Word offsets to interrupt controller */ +#define RVISS_INTC_IRQ_MASKED_STATUS 0 +#define RVISS_INTC_IRQ_UNMASKED_STATUS 1 +#define RVISS_INTC_IRQ_ENABLE 2 +#define RVISS_INTC_IRQ_DISABLE 3 + +/* IRQ numbers. These can be controlled with ARMulator configuration */ +#define RVISS_INT_FIQ 0 +#define RVISS_INT_SOFT 1 +#define RVISS_INT_RX 2 +#define RVISS_INT_TX 3 +#define RVISS_INT_TIMER_1 4 +#define RVISS_INT_TIMER_2 5 + +static void +rviss_irq_mask(unsigned int irq) +{ + /* writing to EnableClear disables */ + rviss_intc[RVISS_INTC_IRQ_DISABLE] = 1 << irq; +} + +static void +rviss_irq_unmask(unsigned int irq) +{ + /* writing to EnableSet enables */ + rviss_intc[RVISS_INTC_IRQ_ENABLE] = 1 << irq; +} + +/* RVISS default interrupt controller irq chip definition */ +static struct irqchip rviss_irq_chip = { + .ack = rviss_irq_mask, + .mask = rviss_irq_mask, + .unmask = rviss_irq_unmask, +}; + +/* RVISS machine_desc.init_irq */ +static void __init +rviss_init_irq(void) +{ + unsigned int irq; + + request_resource(&iomem_resource, &irq_resource); + for (irq = 0; irq <= 5; ++irq) + { + set_irq_chip(irq, &rviss_irq_chip); + set_irq_handler(irq, do_level_IRQ); + set_irq_flags(irq, IRQF_VALID); + } +} + +/* Virtual address of RVISS default timer */ +static volatile unsigned long *rviss_tc = (volatile void *)0xea800000; + +/* Again - the ARMulator documentation is a bit terse about the timer. + * Better consult the reference peripheral spec. The registers are: + * + * base + 0x00: Timer 1 load register, rw + * base + 0x04: Timer 1 value register, ro + * base + 0x08: Timer 1 control register, rw + * base + 0x0c: Timer 1 clear register, wo + * base + 0x20: Timer 2 load register, rw + * base + 0x24: Timer 2 value register, ro + * base + 0x28: Timer 2 control register, rw + * base + 0x2c: Timer 2 clear register, wo + * + * The load and value registers are clear enough: load register is the + * value from which we count to zero and value register tells the + * current count. + * + * The control register has bits: + * + * 7: enable, 0=timer disabled, 1=timer enabled + * 6: mode, 0=free running, 1=periodic + * 3,2: prescale, 00=1, 01=16, 10=256 + * + */ + +/* Word offsets to timer */ +#define RVISS_TIMER_1_LOAD 0 +#define RVISS_TIMER_1_VALUE 1 +#define RVISS_TIMER_1_CONTROL 2 +#define RVISS_TIMER_1_CLEAR 3 + +/* Control register bits */ +#define RVISS_TIMER_CONTROL_ENABLE 0x80 +#define RVISS_TIMER_CONTROL_PERIODIC 0x40 +#define RVISS_TIMER_CONTROL_PRE_SCALE_16 0x04 +#define RVISS_TIMER_CONTROL_PRE_SCALE_256 0x08 + +/* RVISS timer interrupt handler */ +static irqreturn_t +rviss_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + write_seqlock(&xtime_lock); + rviss_tc[RVISS_TIMER_1_CLEAR] = 0; /* clear */ + timer_tick(regs); + write_sequnlock(&xtime_lock); + return IRQ_HANDLED; +} + +/* RVISS timer interrupt definition */ +static struct irqaction rviss_timer_irq = { + .name = "RVISS timer tick", + .flags = SA_INTERRUPT | SA_TIMER, + .handler = rviss_timer_interrupt, +}; + +/* Armulator default CPU clock is 20MHz and bus runs at 1/3 + * I've been running with 100-300MHz CPU clocks. + * ARM11 models seem to have BCLK=FCLK? + * Needs to match CLOCK_TICK_RATE in timex.h + */ +#define RVISS_BUS_CLK 117600000 /* in Hz */ +#define RVISS_BUS_CLK_MHZ_X10 1176 + +/* The timer counter register is 16 bits. We want to generate the interrupt + * at HZ frequency, i.e. we want the timer to be able to count 1/HZ period. + * If we count with 200MHz system clock a 5ms period cannot be counted with + * 16 bit register. If we want prescale with 16 we need to keep HZ on the + * level of clock MHz. Otherwise we need to prescale with 256. + * But 330MHz prescaled with 256 does not give integer tick count + * with any integer HZ. + * period=1/HZ, tick=16/BCLK, count=period/tick=(1/HZ)/(16/BCLK)=BCLK/16/HZ + * e.g. HZ=330, period=3 1/3 ms, BCLK=330MHz, tick=3 1/3 ns => count=62500 + */ +#define RVISS_TIMER_PERIOD_TICKS ((RVISS_BUS_CLK) / 16 / (HZ)) + +/* RVISS system_timer.init */ +static void __init +rviss_timer_init(void) +{ + /* Lets use timer 1 */ + setup_irq(RVISS_INT_TIMER_1, &rviss_timer_irq); + /* disable while setting the load register */ + rviss_tc[RVISS_TIMER_1_CONTROL] = 0; + /* set the reload value */ + rviss_tc[RVISS_TIMER_1_LOAD] = RVISS_TIMER_PERIOD_TICKS; + /* Enable timer, periodic mode, prescale by 16 */ + rviss_tc[RVISS_TIMER_1_CONTROL] + = (RVISS_TIMER_CONTROL_ENABLE + | RVISS_TIMER_CONTROL_PERIODIC + | RVISS_TIMER_CONTROL_PRE_SCALE_16); +} + +/* RVISS system_timer.offset, returns time since last timer tick, in usecs. + * This is called with interrupts disabled. + * + * Obvious implementation would just read the value register. + * + * Since this offset should be in sync with timer_tick() calls we + * should also try to account for the possible condition that the + * terminal count has already been reached and we have the timer interrupt + * pending but have not yet called timer_tick(). In this case we add one + * complete period to the returned offset. + * + * However, there is no way to atomically read the interrupt status and timer + * value. So we read the value register twice to check for reload. + */ +static unsigned long +rviss_timer_offset(void) +{ + unsigned long tick1, tick2, ticks; + unsigned long irqstat; + + /* How can reads and reload get interleaved? + * + * 1) No pending IRQ, no reload + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + * + * 2) IRQ pending, no reload + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + * + * 3) A reload detected, IRQ status does not matter + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + */ + tick1 = rviss_tc[RVISS_TIMER_1_VALUE]; + irqstat = rviss_intc[RVISS_INTC_IRQ_UNMASKED_STATUS]; + tick2 = rviss_tc[RVISS_TIMER_1_VALUE]; + /* the value counts down so if second read is larger we reloaded */ + if (tick2 > tick1) + { + /* There was a reload between the reads, add one period. + * It is of no use to check the IRQ status as the read + * might have happened before reload and we know from + * the tick mismatch that the terminal count has been + * reached. + */ + ticks = 2 * RVISS_TIMER_PERIOD_TICKS - tick2; + } + else + { + /* There was no reload between the reads. + * Now we can just check IRQ status to see whether one + * period needs to be added. It is possible that the + * reload happens after tick2 read, but in this case tick2 + * value should be almost zero, i.e. we do not get the + * "off by one period" error into our offset. + */ + ticks = ((irqstat & (1 << RVISS_INT_TIMER_1)) ? 1 : 2) + * RVISS_TIMER_PERIOD_TICKS - tick2; + } + /* We count with BCLK/16 frequency, i.e. one tick is 16/BCLK sec. + * 1MHz period is 1us. + */ + return 160 * ticks / RVISS_BUS_CLK_MHZ_X10; +} + +struct sys_timer rviss_timer = { + .init = rviss_timer_init, + .offset = rviss_timer_offset, +}; + +/* RVISS memory map can be controlled via config files. + * By default interrupt controller is at 0x0a000000 + */ +MACHINE_START(RVISS, "RealView Instruction Set Simulator (a.k.a. ARMulator)") + /* Maintainer: Nokia Research Center */ + .phys_io = 0x0a000000, + .io_pg_offst = ((0xea000000) >> 18) & 0xfffc, + .map_io = rviss_map_io, + .init_irq = rviss_init_irq, + .timer = &rviss_timer, + .init_machine = rviss_init, +MACHINE_END diff -urN linux-2.6.16.9/arch/arm/mach-rviss/rviss.c~ linux-2.6.16.9-apm/arch/arm/mach-rviss/rviss.c~ --- linux-2.6.16.9/arch/arm/mach-rviss/rviss.c~ 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/arch/arm/mach-rviss/rviss.c~ 2006-05-02 11:39:22.000000000 +0300 @@ -0,0 +1,475 @@ +/* -*- linux-c -*- + * linux/arch/arm/mach-rviss/rviss.c + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Support for ARM RealView Instruction Set Simulator + * + * Written based on ARMulator documentation: + * + * The RVISS user guide + * http://www.arm.com/pdfs/DUI0207C_realview_armulator_iss_ug.pdf + * ARM application note 32 + * http://www.arm.com/pdfs/AppNote32_ARMulator.zip + * Reference Peripheral Specification + * http://www.arm.com/pdfs/DDI0062D_refper-spec.pdf + * + */ + +#include /* ARRAY_SIZE etc */ +#include /* __init etc */ +#include /* struct resource */ +#include /* struct list_head needed by struct irqchip */ +#include /* irqreturn_t etc */ +#include /* struct console etc */ +#include /* struct tty_struct etc */ +#include /* PAGE_SHIFT, needed by __phys_to_pfn */ +#include /* SZ_... */ +#include /* struct map_desc */ +#include /* struct irqchip */ +#include /* timer_tick() */ +#include /* MACHINE_START */ +#include /* MACH_TYPE_RVISS */ + +static volatile unsigned long *rviss_tube = (volatile void *)0xed800020; + +static void +rviss_tube_write(const char *s, + unsigned count) +{ + int i; + for (i = 0; i < count; ++i) + { + /* Seems that '\r' clears the line just written to the + * RealView debugger StdIO - lets just skip em.. + */ + if (*s != '\r') + *rviss_tube = *s; + ++s; + } +} + +static int +rviss_tty_open(struct tty_struct *tty, struct file *filp) +{ + return 0; +} + +static int +rviss_tty_write(struct tty_struct *tty, const unsigned char *buf, int len) +{ + rviss_tube_write(buf, len); + return len; +} + +static int +rviss_tty_write_room(struct tty_struct *tty) +{ + return 512; +} + +static int +rviss_tty_chars_in_buffer (struct tty_struct *tty) +{ + return 0; +} + +static struct tty_operations rviss_tty_ops = { + .open = rviss_tty_open, + .write = rviss_tty_write, + .write_room = rviss_tty_write_room, + .chars_in_buffer = rviss_tty_chars_in_buffer, +}; + +static struct tty_driver *rviss_tty_driver; + +static struct tty_driver * +rviss_console_device(struct console *c, int *index) +{ + *index = c->index; + return rviss_tty_driver; +} + +static void +rviss_console_write(struct console *co, + const char *s, + unsigned int count) +{ + rviss_tube_write(s, count); +} + +static int __init +rviss_tty_init(void) +{ + int err; + struct tty_driver *driver; + + driver = alloc_tty_driver(1); + if (!driver) + return -ENOMEM; + driver->driver_name = "tube"; + driver->name = "ttyRVISS"; + driver->major = 666; + driver->minor_start = 0; + driver->type = TTY_DRIVER_TYPE_SYSTEM; + driver->subtype = SYSTEM_TYPE_SYSCONS; + driver->init_termios = tty_std_termios; + tty_set_operations(driver, &rviss_tty_ops); + err = tty_register_driver(driver); + if (err) + { + put_tty_driver(driver); + return err; + } + rviss_tty_driver = driver; + return 0; +} +late_initcall(rviss_tty_init); + +static struct console rviss_console = { + .name = "ttyRVISS", + .write = rviss_console_write, + .device = rviss_console_device, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +static int __init +rviss_console_init(void) +{ + register_console(&rviss_console); + return 0; +} +console_initcall(rviss_console_init); + +/* RVISS machine_desc.init_machine */ +static void __init +rviss_init(void) +{ +} + +/* For the time being, use the default physical addresses and + * map them to start at virtual 0xe0000000 + */ +static struct map_desc rviss_io_desc[] __initdata = { + /* Interrupt controller */ + { 0xea000000, __phys_to_pfn(0x0a000000), SZ_4K, MT_DEVICE }, + /* Timer */ + { 0xea800000, __phys_to_pfn(0x0a800000), SZ_4K, MT_DEVICE }, + /* Tube */ + { 0xed800000, __phys_to_pfn(0x0d800000), SZ_4K, MT_DEVICE }, +}; + +/* RVISS machine_desc.map_io */ +static void __init +rviss_map_io(void) +{ + iotable_init(rviss_io_desc, ARRAY_SIZE(rviss_io_desc)); +} + +/* Resource descriptor for the RVISS default interrupt controller model */ +static struct resource irq_resource = { + .name = "IRQ (RVISS interrupt controller)", + .start = 0x0a000000, + .end = 0x0a000200, + .flags = IORESOURCE_MEM, +}; + +/* The virtual address for the interrupt controller */ +static volatile unsigned long *rviss_intc = (volatile void *)0xea000000; + +/* The RVISS documentation is really terse about + * the interrupt controller. It more or less just lists + * the registers: + * + * base + 0x000: IRQ status, ro + * base + 0x004: IRQ raw status, ro + * base + 0x008: IRQ enable read/set, rw + * base + 0x00c: IRQ enable clear, wo + * base + 0x010: IRQ soft, wo + * base + 0x100: FIQ status, ro + * base + 0x104: FIQ raw status, ro + * base + 0x108: FIQ enable read/set, rw + * base + 0x10c: FIQ enable clear, wo + * + * One really needs to consult the "ARM DDI 0062D" + * reference peripheral spec, which lists + * - enable register, ro, 1 means enabled + * - enable set, wo, 1 means enable + * - enable clear, wo, 1 means disable + * - source status, ro, 1 means req active (prior to masking) + * - interrupt request, ro, 1 means req active (after masking) + * - programmed int, wo, generate interrupt + * + * So what would one deduce from the above? Status could be req status + * after masking and raw status before masking. Enable, clear and soft + * are less ambiguous. + * + * The interrupt sources in RVISS are (by default): + * - 0: FIQ + * - 1: soft + * - 2: communication channel rx + * - 3: communiaction channel tx + * - 4: timer 1 + * - 5: timer 2 + */ + +/* Word offsets to interrupt controller */ +#define RVISS_INTC_IRQ_MASKED_STATUS 0 +#define RVISS_INTC_IRQ_UNMASKED_STATUS 1 +#define RVISS_INTC_IRQ_ENABLE 2 +#define RVISS_INTC_IRQ_DISABLE 3 + +/* IRQ numbers. These can be controlled with ARMulator configuration */ +#define RVISS_INT_FIQ 0 +#define RVISS_INT_SOFT 1 +#define RVISS_INT_RX 2 +#define RVISS_INT_TX 3 +#define RVISS_INT_TIMER_1 4 +#define RVISS_INT_TIMER_2 5 + +static void +rviss_irq_mask(unsigned int irq) +{ + /* writing to EnableClear disables */ + rviss_intc[RVISS_INTC_IRQ_DISABLE] = 1 << irq; +} + +static void +rviss_irq_unmask(unsigned int irq) +{ + /* writing to EnableSet enables */ + rviss_intc[RVISS_INTC_IRQ_ENABLE] = 1 << irq; +} + +/* RVISS default interrupt controller irq chip definition */ +static struct irqchip rviss_irq_chip = { + .ack = rviss_irq_mask, + .mask = rviss_irq_mask, + .unmask = rviss_irq_unmask, +}; + +/* RVISS machine_desc.init_irq */ +static void __init +rviss_init_irq(void) +{ + unsigned int irq; + + request_resource(&iomem_resource, &irq_resource); + for (irq = 0; irq <= 5; ++irq) + { + set_irq_chip(irq, &rviss_irq_chip); + set_irq_handler(irq, do_level_IRQ); + set_irq_flags(irq, IRQF_VALID); + } +} + +/* Virtual address of RVISS default timer */ +static volatile unsigned long *rviss_tc = (volatile void *)0xea800000; + +/* Again - the ARMulator documentation is a bit terse about the timer. + * Better consult the reference peripheral spec. The registers are: + * + * base + 0x00: Timer 1 load register, rw + * base + 0x04: Timer 1 value register, ro + * base + 0x08: Timer 1 control register, rw + * base + 0x0c: Timer 1 clear register, wo + * base + 0x20: Timer 2 load register, rw + * base + 0x24: Timer 2 value register, ro + * base + 0x28: Timer 2 control register, rw + * base + 0x2c: Timer 2 clear register, wo + * + * The load and value registers are clear enough: load register is the + * value from which we count to zero and value register tells the + * current count. + * + * The control register has bits: + * + * 7: enable, 0=timer disabled, 1=timer enabled + * 6: mode, 0=free running, 1=periodic + * 3,2: prescale, 00=1, 01=16, 10=256 + * + */ + +/* Word offsets to timer */ +#define RVISS_TIMER_1_LOAD 0 +#define RVISS_TIMER_1_VALUE 1 +#define RVISS_TIMER_1_CONTROL 2 +#define RVISS_TIMER_1_CLEAR 3 + +/* Control register bits */ +#define RVISS_TIMER_CONTROL_ENABLE 0x80 +#define RVISS_TIMER_CONTROL_PERIODIC 0x40 +#define RVISS_TIMER_CONTROL_PRE_SCALE_16 0x04 +#define RVISS_TIMER_CONTROL_PRE_SCALE_256 0x08 + +/* RVISS timer interrupt handler */ +static irqreturn_t +rviss_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + write_seqlock(&xtime_lock); + rviss_tc[RVISS_TIMER_1_CLEAR] = 0; /* clear */ + timer_tick(regs); + write_sequnlock(&xtime_lock); + return IRQ_HANDLED; +} + +/* RVISS timer interrupt definition */ +static struct irqaction rviss_timer_irq = { + .name = "RVISS timer tick", + .flags = SA_INTERRUPT | SA_TIMER, + .handler = rviss_timer_interrupt, +}; + +/* Armulator default CPU clock is 20MHz and bus runs at 1/3 + * I've been running with 100-300MHz CPU clocks. + * ARM11 models seem to have BCLK=FCLK? + * Needs to match CLOCK_TICK_RATE in timex.h + */ +#define RVISS_BUS_CLK 330000000 /* in Hz */ +#define RVISS_BUS_CLK_MHZ 330 + +/* The timer counter register is 16 bits. We want to generate the interrupt + * at HZ frequency, i.e. we want the timer to be able to count 1/HZ period. + * If we count with 200MHz system clock a 5ms period cannot be counted with + * 16 bit register. If we want prescale with 16 we need to keep HZ on the + * level of clock MHz. Otherwise we need to prescale with 256. + * But 330MHz prescaled with 256 does not give integer tick count + * with any integer HZ. + * period=1/HZ, tick=16/BCLK, count=period/tick=(1/HZ)/(16/BCLK)=BCLK/16/HZ + * e.g. HZ=330, period=3 1/3 ms, BCLK=330MHz, tick=3 1/3 ns => count=62500 + */ +#define RVISS_TIMER_PERIOD_TICKS ((RVISS_BUS_CLK) / 16 / (HZ)) + +/* RVISS system_timer.init */ +static void __init +rviss_timer_init(void) +{ + /* Lets use timer 1 */ + setup_irq(RVISS_INT_TIMER_1, &rviss_timer_irq); + /* disable while setting the load register */ + rviss_tc[RVISS_TIMER_1_CONTROL] = 0; + /* set the reload value */ + rviss_tc[RVISS_TIMER_1_LOAD] = RVISS_TIMER_PERIOD_TICKS; + /* Enable timer, periodic mode, prescale by 16 */ + rviss_tc[RVISS_TIMER_1_CONTROL] + = (RVISS_TIMER_CONTROL_ENABLE + | RVISS_TIMER_CONTROL_PERIODIC + | RVISS_TIMER_CONTROL_PRE_SCALE_16); +} + +/* RVISS system_timer.offset, returns time since last timer tick, in usecs. + * This is called with interrupts disabled. + * + * Obvious implementation would just read the value register. + * + * Since this offset should be in sync with timer_tick() calls we + * should also try to account for the possible condition that the + * terminal count has already been reached and we have the timer interrupt + * pending but have not yet called timer_tick(). In this case we add one + * complete period to the returned offset. + * + * However, there is no way to atomically read the interrupt status and timer + * value. So we read the value register twice to check for reload. + */ +static unsigned long +rviss_timer_offset(void) +{ + unsigned long tick1, tick2, ticks; + unsigned long irqstat; + + /* How can reads and reload get interleaved? + * + * 1) No pending IRQ, no reload + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + * + * 2) IRQ pending, no reload + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + * + * 3) A reload detected, IRQ status does not matter + * + * reload reload reload + * | | | + * v v v + * ----------+----------+----------+----- + * ^ ^ + * | | + * t1 t2 + */ + tick1 = rviss_tc[RVISS_TIMER_1_VALUE]; + irqstat = rviss_intc[RVISS_INTC_IRQ_UNMASKED_STATUS]; + tick2 = rviss_tc[RVISS_TIMER_1_VALUE]; + /* the value counts down so if second read is larger we reloaded */ + if (tick2 > tick1) + { + /* There was a reload between the reads, add one period. + * It is of no use to check the IRQ status as the read + * might have happened before reload and we know from + * the tick mismatch that the terminal count has been + * reached. + */ + ticks = 2 * RVISS_TIMER_PERIOD_TICKS - tick2; + } + else + { + /* There was no reload between the reads. + * Now we can just check IRQ status to see whether one + * period needs to be added. It is possible that the + * reload happens after tick2 read, but in this case tick2 + * value should be almost zero, i.e. we do not get the + * "off by one period" error into our offset. + */ + ticks = ((irqstat & (1 << RVISS_INT_TIMER_1)) ? 1 : 2) + * RVISS_TIMER_PERIOD_TICKS - tick2; + } + /* We count with BCLK/16 frequency, i.e. one tick is 16/BCLK sec. + * 1MHz period is 1us. + */ + return 16 * ticks / RVISS_BUS_CLK_MHZ; +} + +struct sys_timer rviss_timer = { + .init = rviss_timer_init, + .offset = rviss_timer_offset, +}; + +/* RVISS memory map can be controlled via config files. + * By default interrupt controller is at 0x0a000000 + */ +MACHINE_START(RVISS, "RealView Instruction Set Simulator (a.k.a. ARMulator)") + /* Maintainer: Nokia Research Center */ + .phys_io = 0x0a000000, + .io_pg_offst = ((0xea000000) >> 18) & 0xfffc, + .map_io = rviss_map_io, + .init_irq = rviss_init_irq, + .timer = &rviss_timer, + .init_machine = rviss_init, +MACHINE_END diff -urN linux-2.6.16.9/arch/arm/Makefile linux-2.6.16.9-apm/arch/arm/Makefile --- linux-2.6.16.9/arch/arm/Makefile 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/arch/arm/Makefile 2006-04-24 09:45:45.000000000 +0300 @@ -105,6 +105,7 @@ machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 + machine-$(CONFIG_ARCH_RVISS) := rviss ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff -urN linux-2.6.16.9/arch/arm/mm/Kconfig linux-2.6.16.9-apm/arch/arm/mm/Kconfig --- linux-2.6.16.9/arch/arm/mm/Kconfig 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/arch/arm/mm/Kconfig 2006-04-24 09:56:20.000000000 +0300 @@ -11,7 +11,7 @@ # ARM610 config CPU_ARM610 bool "Support ARM610 processor" - depends on ARCH_RPC + depends on ARCH_RPC || ARCH_RVISS select CPU_32v3 select CPU_CACHE_V3 select CPU_CACHE_VIVT @@ -44,8 +44,8 @@ # ARM720T config CPU_ARM720T - bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR - default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X + bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && (ARCH_INTEGRATOR || ARCH_RVISS) + default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X && !ARCH_RVISS select CPU_32v4 select CPU_ABRT_LV4T select CPU_CACHE_V4 @@ -62,7 +62,7 @@ # ARM920T config CPU_ARM920T bool "Support ARM920T processor" if !ARCH_S3C2410 - depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 + depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 || ARCH_RVISS default y if ARCH_S3C2410 || ARCH_AT91RM9200 select CPU_32v4 select CPU_ABRT_EV4T @@ -83,7 +83,7 @@ # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR - depends on ARCH_LH7A40X || ARCH_INTEGRATOR + depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_RVISS default y if ARCH_LH7A40X select CPU_32v4 select CPU_ABRT_EV4T @@ -102,7 +102,7 @@ # ARM925T config CPU_ARM925T bool "Support ARM925T processor" if ARCH_OMAP1 - depends on ARCH_OMAP15XX + depends on ARCH_OMAP15XX || ARCH_RVISS default y if ARCH_OMAP15XX select CPU_32v4 select CPU_ABRT_EV4T @@ -121,8 +121,8 @@ # ARM926T config CPU_ARM926T bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_RVISS + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_CACHE_VIVT @@ -139,7 +139,7 @@ # ARM1020 - needs validating config CPU_ARM1020 bool "Support ARM1020T (rev 0) processor" - depends on ARCH_INTEGRATOR + depends on ARCH_INTEGRATOR || ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV4T select CPU_CACHE_V4WT @@ -156,7 +156,7 @@ # ARM1020E - needs validating config CPU_ARM1020E bool "Support ARM1020E processor" - depends on ARCH_INTEGRATOR + depends on ARCH_INTEGRATOR || ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV4T select CPU_CACHE_V4WT @@ -168,7 +168,7 @@ # ARM1022E config CPU_ARM1022 bool "Support ARM1022E processor" - depends on ARCH_INTEGRATOR + depends on ARCH_INTEGRATOR || ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV4T select CPU_CACHE_VIVT @@ -185,7 +185,7 @@ # ARM1026EJ-S config CPU_ARM1026 bool "Support ARM1026EJ-S processor" - depends on ARCH_INTEGRATOR + depends on ARCH_INTEGRATOR || ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 select CPU_CACHE_VIVT @@ -200,7 +200,7 @@ # SA110 config CPU_SA110 - bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC + bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && (ARCH_RPC || ARCH_RVISS) default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI select CPU_32v3 if ARCH_RPC select CPU_32v4 if !ARCH_RPC @@ -221,8 +221,8 @@ # SA1100 config CPU_SA1100 bool - depends on ARCH_SA1100 - default y + depends on ARCH_SA1100 || ARCH_RVISS + default y if !ARCH_RVISS select CPU_32v4 select CPU_ABRT_EV4 select CPU_CACHE_V4WB @@ -232,8 +232,8 @@ # XScale config CPU_XSCALE bool - depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 - default y + depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 || ARCH_RVISS + default y if !ARCH_RVISS select CPU_32v5 select CPU_ABRT_EV5T select CPU_CACHE_VIVT @@ -242,7 +242,7 @@ # ARMv6 config CPU_V6 bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_RVISS select CPU_32v6 select CPU_ABRT_EV6 select CPU_CACHE_V6 diff -urN linux-2.6.16.9/arch/arm/tools/mach-types linux-2.6.16.9-apm/arch/arm/tools/mach-types --- linux-2.6.16.9/arch/arm/tools/mach-types 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/arch/arm/tools/mach-types 2006-04-24 09:56:53.000000000 +0300 @@ -969,3 +969,4 @@ fujitsu_wimaxsoc MACH_FUJITSU_WIMAXSOC FUJITSU_WIMAXSOC 956 dualpcmodem MACH_DUALPCMODEM DUALPCMODEM 957 gesbc9312 MACH_GESBC9312 GESBC9312 958 +rviss ARCH_RVISS RVISS 999 diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/debug-macro.S linux-2.6.16.9-apm/include/asm-arm/arch-rviss/debug-macro.S --- linux-2.6.16.9/include/asm-arm/arch-rviss/debug-macro.S 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/debug-macro.S 2006-02-28 19:00:56.000000000 +0200 @@ -0,0 +1,41 @@ +/* linux/include/asm-arm/arch-rviss/debug-macro.S + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Debug macros for ARM RealView Instruction Set Simulator + * Uses the RVISS tube device + */ + + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x0d000000 @ physical base address + movne \rx, #0xed000000 @ virtual base + orr \rx, \rx, #0x00800000 + orr \rx, \rx, #0x00000020 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx + .endm diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/dma.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/dma.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/dma.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/dma.h 2006-02-28 19:06:56.000000000 +0200 @@ -0,0 +1,26 @@ +/* linux/include/asm-arm/arch-rviss/dma.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 + +#endif diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/entry-macro.S linux-2.6.16.9-apm/include/asm-arm/arch-rviss/entry-macro.S --- linux-2.6.16.9/include/asm-arm/arch-rviss/entry-macro.S 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/entry-macro.S 2006-02-28 19:02:18.000000000 +0200 @@ -0,0 +1,45 @@ +/* include/asm-arm/arch-rviss/entry-macro.S + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Low-level IRQ helper macros for RVISS + */ + + /* Hohum? + */ + .macro disable_fiq + .endm + + /* Called by IRQ handler to get interrupt line + * We get the lsb from the irq status mask + * Order is FIQ, soft, rx, tx, t1, t2 + * So e.g. rx can in principle starve tx. + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \base, #0xea000000 /* virtual INTC base */ + ldr \irqstat, [\base] /* IRQ status register, mask of pending */ + mov \irqnr, #0 +1001: tst \irqstat, #1 + bne 1002f + add \irqnr, \irqnr, #1 + movs \irqstat, \irqstat, lsr # 1 + bne 1001b +1002: + .endm + + .macro irq_prio_table + .endm diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/hardware.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/hardware.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/hardware.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/hardware.h 2006-02-28 19:03:02.000000000 +0200 @@ -0,0 +1,26 @@ +/* linux/include/asm-arm/arch-rviss/hardware.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* nothing? */ + +#endif + diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/io.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/io.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/io.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/io.h 2006-02-28 19:04:58.000000000 +0200 @@ -0,0 +1,29 @@ +/* linux/include/asm-arm/arch-rviss/io.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +/* Needed? */ +#define IO_SPACE_LIMIT 0xffff +/* inb/outb need this */ +#define __io(a) ((void __iomem *)(a)) + +#endif + diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/irqs.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/irqs.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/irqs.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/irqs.h 2006-02-28 19:05:13.000000000 +0200 @@ -0,0 +1,35 @@ +/* linux/include/asm-arm/arch-rviss/irqs.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* IRQ numbers - not needed for Linux kernel proper + */ +#define INT_FIQ 0 +#define INT_SOFT 1 +#define INT_RX 2 +#define INT_TX 3 +#define INT_TIMER_1 4 +#define INT_TIMER_2 5 + +/* This is needed for the Linux kernel */ +#define NR_IRQS 6 + +#endif diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/memory.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/memory.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/memory.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/memory.h 2006-02-28 19:05:29.000000000 +0200 @@ -0,0 +1,34 @@ +/* linux/include/asm-arm/arch-rviss/memory.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical RAM offset for kernel use + */ +#define PHYS_OFFSET UL(0xc0000000) + +/* Mapping between virtual and DMAble + * Used to provide deprecated functions + */ +#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET) + +#endif diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/param.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/param.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/param.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/param.h 2006-05-17 15:48:13.000000000 +0300 @@ -0,0 +1,30 @@ +/* linux/include/asm-arm/arch-rviss/param.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_PARAM_H +#define __ASM_ARCH_PARAM_H + +/* Should timer tick count and HZ match exactly? If my timer + * clock source is 330MHz I do not get nice integer tick counts + * for integer HZ with prescaler 256. With 300MHz I can use e.g. 5^3. + */ +#define HZ 200 + +#endif /* __ASM_ARCH_PARAM_H */ + diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/param.h~ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/param.h~ --- linux-2.6.16.9/include/asm-arm/arch-rviss/param.h~ 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/param.h~ 2006-04-25 23:47:23.000000000 +0300 @@ -0,0 +1,30 @@ +/* linux/include/asm-arm/arch-rviss/param.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_PARAM_H +#define __ASM_ARCH_PARAM_H + +/* Should timer tick count and HZ match exactly? If my timer + * clock source is 330MHz I do not get nice integer tick counts + * for integer HZ with prescaler 256. With 300MHz I can use e.g. 5^3. + */ +#define HZ 330 + +#endif /* __ASM_ARCH_PARAM_H */ + diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/system.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/system.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/system.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/system.h 2006-02-28 19:05:57.000000000 +0200 @@ -0,0 +1,33 @@ +/* linux/include/asm-arm/arch-rviss/system.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/timex.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/timex.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/timex.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/timex.h 2006-05-17 16:09:16.000000000 +0300 @@ -0,0 +1,27 @@ +/* linux/include/asm-arm/arch-rviss/timex.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* Our timer counts with bus clock / 16 + */ +#define CLOCK_TICK_RATE (117600000 / 16) + +#endif /* __ASM_ARCH_TIMEX_H */ diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/timex.h~ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/timex.h~ --- linux-2.6.16.9/include/asm-arm/arch-rviss/timex.h~ 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/timex.h~ 2006-04-25 23:47:13.000000000 +0300 @@ -0,0 +1,27 @@ +/* linux/include/asm-arm/arch-rviss/timex.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* Our timer counts with bus clock / 16 + */ +#define CLOCK_TICK_RATE (330000000 / 16) + +#endif /* __ASM_ARCH_TIMEX_H */ diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/uncompress.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/uncompress.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/uncompress.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/uncompress.h 2006-02-28 19:06:17.000000000 +0200 @@ -0,0 +1,35 @@ +/* linux/include/asm-arm/arch-rviss/uncompress.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* Output to tube + */ +static void putstr(const char *s) +{ + volatile unsigned long *rviss_tube = (volatile void *)0xed800020; + while (*s) { + *rviss_tube = *s; + ++s; + } +} + +/* Nothing needed + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() diff -urN linux-2.6.16.9/include/asm-arm/arch-rviss/vmalloc.h linux-2.6.16.9-apm/include/asm-arm/arch-rviss/vmalloc.h --- linux-2.6.16.9/include/asm-arm/arch-rviss/vmalloc.h 1970-01-01 02:00:00.000000000 +0200 +++ linux-2.6.16.9-apm/include/asm-arm/arch-rviss/vmalloc.h 2006-02-28 19:06:25.000000000 +0200 @@ -0,0 +1,25 @@ +/* linux/include/asm-arm/arch-rviss/vmalloc.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Antti P Miettinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff -urN linux-2.6.16.9/Makefile linux-2.6.16.9-apm/Makefile --- linux-2.6.16.9/Makefile 2006-04-19 09:10:14.000000000 +0300 +++ linux-2.6.16.9-apm/Makefile 2006-04-24 09:57:53.000000000 +0300 @@ -152,7 +152,7 @@ -e s/arm.*/arm/ -e s/sa110/arm/ \ -e s/s390x/s390/ -e s/parisc64/parisc/ \ -e s/ppc.*/powerpc/ ) - +SUBARCH := arm # Cross compiling and selecting different set of gcc/bin-utils # --------------------------------------------------------------------------- # @@ -173,7 +173,7 @@ # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile ARCH ?= $(SUBARCH) -CROSS_COMPILE ?= +CROSS_COMPILE ?= arm-linux- # Architecture as present in compile.h UTS_MACHINE := $(ARCH)